As integrated circuits (ICs), especially CMOS circuits, are reduced in size into the sub-micron range with ever thinner oxide layers, shallower junctions, more lightly doped structures, and silicided diffusions, the structures become ever more susceptible to ESD induced failures. Human or mechanical handling produce static charges that can and do cause destructive failure in such ICs. At most risk to such failure are those components that are electrically connected to terminals or pads leading off the printed circuit board carrying the components. Active devices are usually more prone to ESD failures. So the gates, the drains, the source (and the bases, collectors and emitters) of a CMOS (complementary metal over silicon) buffer, and the drains, sources, and gates of such devices that are electrically connected to power and ground rails are most susceptible.
Generally, ESD events produce voltages that permanently damage thin oxide insulting layers and/or uneven current densities that damage junctions and/or diffusion profiles in small areas. These mechanisms have been well documented in the art. For example, see “Achieving Uniform NMOS Device Power Distribution for Sub-micron ESD Reliability,” by C Duvvury and C. Diaz, and T. Haddock, in IEDM Technical Digest, 1992.
Prior art ESD protect circuits include series resistors, filter capacitors, and Zener or other such breakdown devices employed at the terminals to limit the effect of the ESD event. These protection techniques are designed, inter alia, with marginal success to trigger at ESD voltages higher than the typical operating voltages of the product itself so that the ESD protection does not interfere with the typical product functional operation.
It is well known in the art to apply NMOS devices, herein called ESD NMOS, to provide circuit characteristics that protect functional circuitry from ESD failures. Since the protection mechanism is well known, only a brief outline of the protection follows.
ESD NMOS devices demonstrate a latching type of breakdown, sometimes referred to as “snap-back,” due to the negative resistance characteristic of the current versus voltage curve of the device. A strong electric field across the depletion zone in the drain substrate will cause it to avalanche. This forward biases the source junction and the NMOS snaps-back to a low impedance drain to source to conduct the ESD current and limit the ESD voltage. Lateral bipolar transistors (that may exist as parasitic transistors, see item 30 FIG. 1), in parallel with the ESD device, may help in the ESD protection. Circuits employing these devices often have resistor/capcitor (RC) circuits that are used to trigger the ESD device. For example, see U.S. Pat. No. 5,959,488 invented by Shi-Tron Lin.
In particular, ESD events on the power (Vcc) and/or ground (gnd) have been a continuing problem. In particular, since the power rail can have a wide range of capacitance connected to it, due to the many different circuit families and applications, the ESD signal edges may be quite different in the different conditions and these differences will compromise the effects of fixed RC trigger circuits. Designing one RC to accommodate the wide variety of environments would require too much chip space—it is inefficient. Zeners and other such avalanche break down devices suffer from process variations and can leak or improperly breakdown and interfere with typical product operations.
The present invention provides a trigger circuit that: is efficient in chip space; is effective with the wide variety of capacitances and other such environmental conditions; is applicable to ESD NMOS or NPN transistors; can be designed with low and programmable (adjustable) trigger voltages that protect the product circuits; and can be designed to not interfere with the normal product function over the specified environmental conditions for the product.